A typical configuration example of a multiprocessor (parallel processor) system of this type will be shown in FIG. 9 (refer to Non-Patent Document 1). The multiprocessor (parallel processor) system includes a plurality of symmetrical or asymmetrical processors and co-processors. In this system, a memory and a peripheral IO are shared by the processors.
Co-processors (co-processors) are classified into the following two types:
co-processors that assists processors by taking charge of specific processing (audio, video, or wireless processing, or an arithmetic operation such as a floating-point arithmetic or an arithmetic operation of an FET (Fast Fourier Transform) or the like); and
co-processors that serve as hardware accelerators that perform whole processing necessary for the specific processing (audio, video, wireless processing, or the like)
In the multiprocessor including plurality processors, a co-processor may be shared by the processors like the memory, or the co-processor may be exclusively used locally by a processor.
An example shown in FIG. 9 is a configuration in which a co-processor is exclusively used locally by a processor. Then, an example of an LSI configuration using a configurable processor MeP (Media embedded Processor) technique is shown.
FIG. 10 is a simplified diagram for explaining the configuration in FIG. 9. As shown in FIG. 10, a processor 201A and a processor 201B are tightly coupled to co-processors 203A and 203B for specific applications through local buses for the processors, respectively. Local memories 202A and 202B store instructions and operation data to be executed by the processors 201A and 201B, respectively.
A parallel processing device of a configuration in which a multiprocessor and peripheral hardware (composed of co-processors and various peripheral devices) connected to the multiprocessor are efficiently emphasized is disclosed in Patent Document 1. FIG. 11 is a diagram showing a configuration of a CPU disclosed in Patent Document 1. Referring to FIG. 11, the configuration includes a plurality of processor units P0 to P3 each of which executes a task or a thread. The configuration includes a CPU 10 connected to co-processors 130a and 130b and peripheral hardware composed of peripheral devices 40a to 40d. Each processor unit that executes a task or a thread asks the peripheral hardware to process the task or thread according to execution content of the task or thread being executed. FIG. 12 is a simplified diagram of the configuration in FIG. 11. As shown in FIG. 12, the processors P0 to P3, and co-processors 130a and 130b are connected to a common bus. Then, the processors P0 to P3 access the co-processors 130a and 130b through the common bus.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P-2006-260377A
[Non-Patent Document 1]
Toshiba Semiconductor Product Catalog General Information on Mep (Media embedded Processor) Internet URL:<http://www.semicon.toshiba.co.jp/docs/calalog/ja/BCJ0043_catalog.pdf>